# Table of Contents

- [Introduction | Nintendo 3DS ARM Documentation](#introduction-nintendo-3ds-arm-documentation)
- [Terminology | Nintendo 3DS ARM Documentation](#terminology-nintendo-3ds-arm-documentation)
- [ARM11 MPCore | Nintendo 3DS ARM Documentation](#arm11-mpcore-nintendo-3ds-arm-documentation)
- [About the 3DS CPU(s) | Nintendo 3DS ARM Documentation](#about-the-3ds-cpu-s-nintendo-3ds-arm-documentation)
- [Core Registers | Nintendo 3DS ARM Documentation](#core-registers-nintendo-3ds-arm-documentation)
- [Privilege Modes | Nintendo 3DS ARM Documentation](#privilege-modes-nintendo-3ds-arm-documentation)
- [APSR and CPSR Flags | Nintendo 3DS ARM Documentation](#apsr-and-cpsr-flags-nintendo-3ds-arm-documentation)
- [The APSR, CPSR, SPSR, and the Difference Between Them | Nintendo 3DS ARM Documentation](#the-apsr-cpsr-spsr-and-the-difference-between-them-nintendo-3ds-arm-documentation)
- [VFP | Nintendo 3DS ARM Documentation](#vfp-nintendo-3ds-arm-documentation)
- [VFP Registers | Nintendo 3DS ARM Documentation](#vfp-registers-nintendo-3ds-arm-documentation)
- [VFP System Registers | Nintendo 3DS ARM Documentation](#vfp-system-registers-nintendo-3ds-arm-documentation)
- [FPSID | Nintendo 3DS ARM Documentation](#fpsid-nintendo-3ds-arm-documentation)
- [FPSCR | Nintendo 3DS ARM Documentation](#fpscr-nintendo-3ds-arm-documentation)
- [ID Code Register | Nintendo 3DS ARM Documentation](#id-code-register-nintendo-3ds-arm-documentation)
- [CP15 | Nintendo 3DS ARM Documentation](#cp15-nintendo-3ds-arm-documentation)
- [Default NaN Mode | Nintendo 3DS ARM Documentation](#default-nan-mode-nintendo-3ds-arm-documentation)
- [Cache Type Register | Nintendo 3DS ARM Documentation](#cache-type-register-nintendo-3ds-arm-documentation)
- [Flush-To-Zero Mode | Nintendo 3DS ARM Documentation](#flush-to-zero-mode-nintendo-3ds-arm-documentation)
- [ARM946E-S | Nintendo 3DS ARM Documentation](#arm946e-s-nintendo-3ds-arm-documentation)
- [Tightly-coupled Memory Size Register | Nintendo 3DS ARM Documentation](#tightly-coupled-memory-size-register-nintendo-3ds-arm-documentation)
- [Glossary | Nintendo 3DS ARM Documentation](#glossary-nintendo-3ds-arm-documentation)

---

# Introduction | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Nintendo 3DS ARM Documentation
==============================

This 'book' will mainly detail the ARM hardware on the 3DS. It will also include examples for certain operations.

Primarily this will act like a small overview for quickly checking information on 3DS-specific ARM stuff.

Secondarily, I made this because I'm a forgetful twat, so now I don't have an excuse.

---

# Terminology | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Terminology
===========

This page details terminology that is commonly used when relating to ARM CPU internals.

*   RAO – Read-As-One
    
    *   Hardware must implement the field as reading as all 1s.
    *   Software can rely on the field reading as all 1s.
    *   This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
*   RAO/SBOP – Read-As-One, Should-Be-One-or-Preserved on writes
    
    *   Hardware must implement the field as Read-as-One, and must ignore writes to the field.
    *   Software can rely on the field reading as all 1s, but must use an SBOP policy to write to the field.
    *   This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
*   RAO/WI – Read-As-One, Writes Ignored
    
    *   Hardware must implement the field as read as Read-as-One, and must ignore writes to the field.
    *   Software can rely on the field reading as all 1s, and on writes being ignored.
    *   This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
*   RAZ – Read-As-Zero
    
    *   Same as RAO, but with 0s instead of 1s.
*   RAZ/SBZP – Read-As-Zero, Should-Be-Zero-or-Preserved on writes
    
    *   Same as RAO/SBOP, but with 0s instead of 1s.
*   RAZ/WI – Read-As-Zero, Writes Ignored
    
    *   Same as RAO/WI, but with 0s instead of 1s.
*   SBO – Should-Be-One
    
    *   Hardware must ignore writes to the field.
    *   Software should write the field as all 1s. If software writes a value that is not all 1s, it must expect an UNPREDICTABLE result.
    *   This description can apply to a single bit that should be written as 1, or to a field that should be written as all 1s.
*   SBOP – Should-Be-One-or-Preserved
    
    *   Hardware must ignore writes to the field.
    *   If software has read the field since the processor implementing the field was last reset and initialized, it should preserve the value of the field by writing the value that it previously read from the field. Otherwise, it should write the field as all 1s.
    *   If software writes a value to the field that is not a value previously read for the field and is not all 1s, it must expect an UNPREDICTABLE result.
    *   This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.
*   SBZ – Should-Be-Zero
    
    *   Hardware must ignore writes to the field.
    *   Software should write the field as all zeroes, otherwise it's considered unpredictable.
    *   Applies to a single bit, or a bit field that should be all zeroes.
*   SBZP – Should-Be-Zero-or-Preserved on writes.
    
    *   Same as SBOP, but with 0s instead of 1s.
*   UNKNOWN
    
    *   Does not contain valid data, and can vary from moment to moment, or instruction to instruction.
    *   An UNKNOWN value must not return information that cannot be accessed at the current or a lower level of privilege using instructions that are not UNPREDICTABLE and do not return UNKNOWN values.
    *   Must not be documented or promoted as having a defined value or effect.
*   UNPREDICTABLE
    
    *   Means the behavior cannot be relied upon. UNPREDICTABLE behavior must not perform any function that cannot be performed at the current or a lower level of privilege using instructions that are not UNPREDICTABLE.
    *   UNPREDICTABLE behavior must not be documented or promoted as having a defined effect.
    *   An instruction that is UNPREDICTABLE can be implemented as UNDEFINED.

---

# ARM11 MPCore | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html#)
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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

ARM11 MPCore
============

This chapter will detail information about the ARM11 MPCore processor in the 3DS.

---

# About the 3DS CPU(s) | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

About the 3DS CPU(s)
====================

*   The 3DS has two processors in it, an ARM11 processor, and an ARM9 processor.
    *   ARM11 MPCore 2x & 2x VFPv2 Co-Processor
    *   ARM946

The ARM11 MPCore processor is a dual-core processor, which has it's cores divided in terms of accessibility and purpose. One core is dedicated solely for system software while the other core is used for applications (e.g. Games and general software); this is the core that applications you create will run on. These cores are commonly referred to in the homebrew community as the _syscore_ and _appcore_.

The ARM9 processor only ever has one process running, which is named Process9. Process9 interacts with the kernel and handles commands from the ARM11 MPCore processor.

Since the MPCore only has VFPv2, this means it doesn't have NEON or any of the fancy floating-point operations that are possible in newer processor models, so this makes things (sort of) simple for us. I'll explain in detail in the respective sections.

When building applications for the 3DS. It is best to pass `-march=armv6k` in your Makefile.

---

# Core Registers | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Core Registers
==============

The ARM processors have 16 core registers.

*   Registers R0-R12:
    *   General purpose
*   Register R13
    *   Used as the stack pointer (SP)
*   Register R14
    *   Used as the link register (LR)
*   Register R15
    *   Used as the program counter (PC)
    *   Unlike some other architectures, the PC can be directly modified by some instructions.

---

# Privilege Modes | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/privilege_modes.html#)
[](https://lioncash.github.io/ARMBook/privilege_modes.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

[](https://lioncash.github.io/ARMBook/privilege_modes.html#)

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Privilege Modes
===============

ARM processors have privilege modes which allow preventing certain operations by an executing process. The privilege modes the CPUs in the 3DS have are the following:

| Mode | Description |
| --- | --- |
| User | Unprivileged mode. Applications normally run in this mode |
| System | Runs applications with elevated privileges. System mode can be viewed as a cross between user and supervisor modes. It provides the privileges of supervisor mode, but shares registers with user mode. |
| FIQ | ARM processors have two types of interrupt types: regular interrupts, and fast interrupts (FIQs). The only difference between fast interrupts and normal interrupts is that fast interrupts can interrupt regular interrupts (kind of a mouthful to say). Since ARM processors do not have non-maskable interrupts (NMIs), FIQs can be disabled when necessary. Interrupts that need to complete very quickly will use this mode. |
| IRQ | Regular interrupt mode. Interrupts that are not time-critical (not requiring clock timing accuracy) will normally use this mode. |
| Supervisor | Privileged mode for the operating system. |
| Abort | This mode is entered whenever an abort exception occurs. |
| Undefined | This mode is entered whenever an undefined instruction exception is signalled. Normally whenever an undefined instruction exception is encountered, the ARM processor will wait and see if any coprocessors are able to handle the instruction. If not, then the undefined instruction vector is taken. Some software can actually utilize this form of exception handling to software emulate undefined coprocessor instructions |

On the ARM11 MPCore both cores run in _user mode_. In user mode, access to certain other registers is not possible (such as a majority of the registers in the CP15 coprocessor). It isn't possible to explicitly switch to a higher privileged mode from user mode.

Note that each mode can also have it's own registers that 'shadow' the original core 15 registers. These are known as _banked registers_. These registers are automatically brought into 'view' (possible to read/write to) whenever the processor changes into modes that have these registers.

Which registers are to be shadowed in a processor mode are different. The table below depicts the registers shadowed per mode in the ARM11 MPCore.

| Mode | Shadowed Registers |
| --- | --- |
| User | No shadowed registers |
| System | Shares registers with user mode |
| Supervisor | SP, LR, CPSR |
| Abort | SP, LR, CPSR |
| Undefined | SP, LR, CPSR |
| IRQ | SP, LR, CPSR |
| FIQ | R8, R9, R10, R11, R12, SP, LR, CPSR |

---

# APSR and CPSR Flags | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html#)
[](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

APSR and CPSR Flags
===================

The CPSR (which contains the APSR):

| 31  | 30  | 29  | 28  | 27  | 26 - 25 | 24  | 23 - 20 | 19 - 16 | 15 - 10 | 9   | 8   | 7   | 6   | 5   | 4 - 0 |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| N   | Z   | C   | V   | Q   | RAZ | J   | Reserved/UNK/SBZP | GE  | RAZ | E   | A   | I   | F   | T   | M\[4:0\] |

  

| Flag | Description |
| --- | --- |
| N (Negative) | Set if the result of a data processing instruction was negative |
| Z (Zero) | Set if the result of an instruction operation is zero |
| C (Carry) | Set if the result of an unsigned operation overflows the 32-bit result register |
| V (Overflow) | Same as the carry flag, but for signed operations |
| Q (Saturation) | Set if saturation occurs during execution of a saturation instruction. This flag is sticky; it must be explicitly cleared by an MSR instruction. |
| J (Jazelle) | Set when the CPU is in Jazelle mode |
| GE (Greater than or Equal) | Used by the SEL instruction for byte selection |
| E (Endian) | Controls the endianness for load/store instructions. When cleared, load/store instructions operate in little-endian. When set, load/store instructions operate in big endian. |
| A (Abort) | Controls whether or not imprecise data aborts are disabled. |
| I (IRQ) | Controls whether or not IRQ interrupts are disabled. |
| F (FIQ) | Controls whether or not FIQ interrupts are disabled. |
| T (Thumb) | Indicates if the processor is in Thumb mode. If set, Thumb mode is active. If cleared, Thumb mode is not active. |
| M (Mode) | Indicates the current processor mode. See table below |

  

This table shows what processor modes correspond to mode bit configurations.

| Bits | Mode |
| --- | --- |
| 10000 | User |
| 10001 | FIQ |
| 10010 | IRQ |
| 10011 | Supervisor |
| 10111 | Abort |
| 11011 | Undefined |
| 11111 | System |

### Notes

* * *

*   Despite the ARM11 MPCore in the 3DS having the Jazelle bit, the 3DS doesn't actually support Jazelle.
    *   **However**, it _does_ support the instruction that attempts to enter Jazelle mode (BXJ). Attempts to use it will make it function like a BX instruction.

---

# The APSR, CPSR, SPSR, and the Difference Between Them | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html#)
[](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

The APSR, CPSR, SPSR, and the Difference Between Them
=====================================================

#### APSR – Application Program Status Register

*   Only holds copies of the ALU status flags (AKA condition code flags).
*   Flags here determine whether or not an instruction is executed, with two exceptions
    *   On ARMv6 and later, GE (Greater than or Equal) flags are present. These are used by the SEL instruction to perform byte selection.
    *   On ARMv5TE, ARMv6 or later, the Q flag is present. This is set by saturation instructions

The APSR on the ARM11 MPCore takes the form:

| 31  | 30  | 29  | 28  | 27  | 26 - 24 | 23 - 20 | 19 - 16 | 15 - 0 |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| N   | Z   | C   | V   | Q   | RAZ/SBZP | Reserved/UNK/SBZP | GE  | Reserved/UNK/SBZP |

  

#### CPSR – Current Program Status Register

*   Contains:
    *   The APSR flags
    *   Current instruction set state
    *   Execution state bits for the Thumb If-Then (IT) instruction (RAZ in the 3DS ARM processors; not capable of executing IT).
    *   Current endianness (E bit, bit 9)
    *   Current processor mode (bits 0 - 4)
    *   Interrupt and asynchronous abort disable bits

The CPSR on the ARM11 MPCore takes the form:

| 31  | 30  | 29  | 28  | 27  | 26 - 25 | 24  | 23 - 20 | 19 - 16 | 15 - 10 | 9   | 8   | 7   | 6   | 5   | 4 - 0 |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| N   | Z   | C   | V   | Q   | RAZ | J   | Reserved/UNK/SBZP | GE  | RAZ | E   | A   | I   | F   | T   | M\[4:0\] |

  

#### SPSR – Saved Program Status Register

*   All processor modes except system and user mode have an SPSR.
*   Records the pre-exception value of the CPSR.
*   Upon taking an exception, the CPSR is copied to the SPSR of the processor mode the exception is taken to.
    *   This is useful because the exception handler is able to restore the CPSR to the value prior to taking the exception, as well as being able to examine the CPSR in general.

---

# VFP | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/vfp/README.html#)
[](https://lioncash.github.io/ARMBook/vfp/README.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Vector Floating Point (VFP) Stuff
=================================

The 3DS ARM11 MPCore contains a floating-point coprocessor extension. This extension is called VFP. VFP has several implementation versions which provide different features; the ARM11 MPCore utilizes VFPv2 (also called VFP11 when referring to the ARM11 implementation of it as a whole).

As such, the 3DS is not capable of using floating-point extensions such as NEON (AKA Advanced SIMD).

---

# VFP Registers | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html#)
[](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

VFP Registers
=============

The VFPv2 architecture contains 16 double-precision (64-bit) registers (d0-d15) that can be subdivided into 32 single-precision (32-bit) registers (s0-s31). The VFPv2 architecture also contains several system registers as well, which are detailed in the next few sections.

---

# VFP System Registers | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html#)
[](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

VFP System Registers
====================

The VFPv2 architecture describes three system registers that _must_ be present in a VFP system.

*   Floating-Point System ID Register (FPSID)
*   Floating-Point Status and Control Register (FPSCR)
*   Floating-Point Exception Register (FPEXC)

To support exceptional conditions, the VFP11 coprocessor provides two additional system registers:

*   Floating-Point Instruction Register (FPINST)
*   Floating-Point Instruction Register (FPINST2)

VFP11 also provides two feature registers.

*   Media and VFP Feature Register 0 (MVFR0)
*   Media and VFP Feature Register 1 (MVFR1)

  
Below is a table detailing basic access information about these registers:

| Register | Access Mode | Access Type | Reset State |
| --- | --- | --- | --- |
| FPSID | Any | RO  | 0x410120B4 |
| FPSCR | Any | R/W | 0x00000000 |
| FPEXC | Privileged | R/W | 0x00000000 |
| FPINST | Privileged | R/W | 0xEE000000 |
| FPINST2 | Privileged | R/W | UNPREDICTABLE |
| MVFR0 | Any | RO  | 0x11111111 |
| MVFR1 | Any | RO  | 0x00000000 |

---

# FPSID | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/vfp/fpsid.html#)
[](https://lioncash.github.io/ARMBook/vfp/fpsid.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

[](https://lioncash.github.io/ARMBook/vfp/fpsid.html#)

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

FPSID - Floating-Point System ID Register
=========================================

*   Read-only register
*   Accessible in privileged and unprivileged modes.
*   Contains information about the VFP11 coprocessor.

Layout:

| 31 - 24 | 23  | 22 - 21 | 20  | 19 - 16 | 15 - 8 | 7 - 4 | 3 - 0 |
| --- | --- | --- | --- | --- | --- | --- | --- |
| Implementer | SW  | Format | SNG | Architecture | Part Number | Variant | Revision |

Bitfields:

| Bit(s) | Meaning | Value |
| --- | --- | --- |
| 31:24 | Implementer | **0x41** (ARM Limited) |
| 23  | Hardware/Software | **0** (Hardware implementation) |
| 22:21 | FSTMX/FLDMX format | **b00** (Format 1) |
| 20  | Precisions Supported | **0** (Single-precision and double-precision) |
| 19:16 | Architecture Version | **b0001** (VFPv2 architecture) |
| 15:8 | Part Number | **0x20** (VFP11) |
| 7:4 | Variant | **0xB** (MPCore VFP Interface) |
| 3:0 | Revision | **0x4** (Fourth version) |

---

# FPSCR | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/vfp/fpscr.html#)
[](https://lioncash.github.io/ARMBook/vfp/fpscr.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

FPSCR - Floating-Point Status and Control Register
==================================================

*   Read/write register
*   Accessible in privileged and unprivileged modes.
*   Contains VFP status and control bits.

Layout:

| 31  | 30  | 29  | 28  | 27 - 26 | 25  | 24  | 23 - 22 | 21 - 20 | 19  | 18 - 16 | 15  | 14 - 13 | 12  | 11  | 10  | 9   | 8   | 7   | 6 - 5 | 4   | 3   | 2   | 1   | 0   |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| N   | Z   | C   | V   | SBZ | DN  | FZ  | Rmode | Stride | SBZ | LEN | IDE | SBZ | IXE | UFE | OFE | DZE | IOE | IDC | SBZ | IXC | UFC | OFC | DZC | IOC |

Bitfields:

| Bit(s) | Name | Meaning |
| --- | --- | --- |
| 31  | N   | Set if comparison produces a _less than_ result |
| 30  | Z   | Set if comparison produces an _equal_ result |
| 29  | C   | Set if comparison produces an _equal, greater than or unordered_ result |
| 28  | V   | Set if comparison produces an _unordered_ result |
| 27:26 | \-  | Should Be Zero |
| 25  | DN  | Default NaN mode enable bit |
| 24  | FZ  | Flush-to-zero mode enable bit |
| 23:22 | Rmode | Rounding mode control field. See table below for possible values |
| 21:20 | Stride | Vector stride |
| 19  | \-  | Should Be Zero |
| 18:16 | LEN | Vector length |
| 15  | IDE | Input Subnormal exception enable bit |
| 14:13 | \-  | Should Be Zero |
| 12  | IXE | Inexact exception enable bit |
| 11  | UFE | Underflow exception enable bit |
| 10  | OFE | Overflow exception enable bit |
| 9   | DZE | Division by Zero exception enable bit |
| 8   | IOE | Invalid Operation exception enable bit |
| 7   | IDC | Input Subnormal cumulative flag |
| 6:5 | \-  | Should Be Zero |
| 4   | IXC | Inexact cumulative flag |
| 3   | UFC | Underflow cumulative flag |
| 2   | OFC | Overflow cumulative flag |
| 1   | DZC | Division by Zero cumulative flag |
| 0   | IOC | Invalid Operation cumulative flag |

Rounding modes:

| Bits | Mode |
| --- | --- |
| b00 | Round to nearest (RN) mode |
| b01 | Round towards plus infinity (RP) mode |
| b10 | Round towards minus infinity (RM) mode |
| b11 | Round towards zero (RZ) mode |

---

# ID Code Register | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html#)
[](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

ID Code Register
================

*   Read only
*   Contains the device ID code.
*   Accessible only in privileged modes.
*   Raw value: **0x41059461**

| Register Bits | Function | Value |
| --- | --- | --- |
| 31:24 | Implementor | **0x41** |
| 23:20 | Variant (reserved) | **0x0** |
| 19:16 | ARM architecture 5TE | **0x5** |
| 15:4 | Primary Part Number | **0x946** |
| 3:0 | Revision (major product revision) | **0x1** |

This register can be accessed via `MRC p15, 0, Rd, c0, c0, {0,3-7}`. It doesn't matter which number is used in the braces, they will all return the same register.

---

# CP15 | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html#)
[](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

CP15
====

This section will detail implementation specific values for the CP15 coprocessor on the 3DS.

---

# Default NaN Mode | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/vfp/default_nan.html#)
[](https://lioncash.github.io/ARMBook/vfp/default_nan.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

[](https://lioncash.github.io/ARMBook/vfp/default_nan.html#)

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[](https://lioncash.github.io/ARMBook/vfp/default_nan.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Default NaN Mode
================

When bit 25 in the FPSCR is set, default NaN mode is enabled. When this mode is enabled, any operation which generates a NaN, or takes a NaN as an input will return the default NaN as the result. Note that enabling this is not IEEE compliant.

Enabling Default NaN Mode:

    VMRS r0, FPSCR
    ORR r0, r0, #(1 << 25)
    VMSR FPSCR, r0
    

Disabling Default NaN Mode:

    VMRS r0, FPSCR
    BIC r0, r0, #(1 << 25)
    VMSR FPSCR, r0
    

### Notes

* * *

*   On the VFPv2 coprocessor, the sign bit of the default NaN is considered `UNKNOWN`.
    *   However, within the VFPv2 implementation used in the 3DS, the sign bit of the default NaN is always positive.
        *   Single-precision default NaN: 0x7fc00000
        *   Double-precision default NaN: 0x7fc0000000000000

---

# Cache Type Register | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html#)
[](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Cache Type Register
===================

*   Read only
*   Contains information about the caches and their architecture.
*   Accessible only in privileged mode.
*   Raw value: **0x0F0D2112**

| Register Bits | Function | Value |
| --- | --- | --- |
| 31:29 | Reserved | b000 |
| 28:25 | Cache Type | b0111 |
| 24  | Harvard/Unified Cache | 1 (defines Harvard cache) |
| 23:22 | Reserved | b00 |
| 21:18 | Data Cache Size | 3 (4KB) |
| 17:15 | Data Cache Associativity | 2 (4-way associative) |
| 14  | Data Cache Absent | 0   |
| 13:12 | Data Cache Words Per Line | b10 (8 words per line) |
| 11:10 | Reserved | b00 |
| 9:6 | Instruction Cache Size | 4 (8KB) |
| 5:3 | Instruction Cache Associativity | 2 (4-way associative) |
| 2   | Instruction Cache Absent | 0   |
| 1:0 | Instruction Cache Words Per Line | b10 (8 words per line) |

This register can be accessed via `MRC p15,0,Rd,c0,c0,1`.

---

# Flush-To-Zero Mode | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html#)
[](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Flush-To-Zero Mode
==================

These enable or disable the flushing of subnormals to zero. Note that enabling this isn't IEEE compliant.

Enabling FTZ:

    VMRS r0, FPSCR
    ORR r0, r0, #(1 << 24)
    VMSR FPSCR, r0
    

Disabling FTZ

    VMRS r0, FPSCR
    BIC r0, r0, #(1 << 24)
    VMSR FPSCR, r0

---

# ARM946E-S | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/arm946e-s/README.html#)
[](https://lioncash.github.io/ARMBook/arm946e-s/README.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/arm946e-s/README.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

ARM946E-S
=========

This chapter will detail specifics relating to the ARM9 processor in the 3DS.

---

# Tightly-coupled Memory Size Register | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html#)
[](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html#)

[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

Tightly-coupled Memory Size Register
====================================

*   Read only
*   Contains information regarding the data and instruction tightly-coupled memory (TCM)
*   Accessible only in privileged modes
*   Raw value: **0x00140180**

| Register Bits | Meaning | Value |
| --- | --- | --- |
| 31:22 | Reserved | b0000000000 |
| 21:18 | Data TCM Size | 5 (16KB) |
| 17:15 | Reserved | b000 |
| 14  | Data TCM Absent | 0   |
| 13:10 | Reserved | b0000 |
| 9:6 | Instruction TCM Size | 6 (32KB) |
| 5:3 | Reserved | b000 |
| 2   | Instruction TCM Absent | 0   |
| 1:0 | Reserved | b00 |

This register can be accessed via `MRC p15, 0, Rd, c0, c0, 2`.

---

# Glossary | Nintendo 3DS ARM Documentation

*   [Introduction](https://lioncash.github.io/ARMBook/index.html)
    *   [**0.1.** About the 3DS CPU(s)](https://lioncash.github.io/ARMBook/about_the_3ds.html)
        
    *   [**0.2.** Terminology](https://lioncash.github.io/ARMBook/terminology.html)
        
*   [**1.** ARM11 MPCore](https://lioncash.github.io/ARMBook/arm11_mpcore/README.html)
    *   [**1.1.** Core Registers](https://lioncash.github.io/ARMBook/registers.html)
        
    *   [**1.2.** Privilege Modes](https://lioncash.github.io/ARMBook/privilege_modes.html)
        
    *   [**1.3.** APSR and CPSR Flags](https://lioncash.github.io/ARMBook/apsr_and_cpsr_flags.html)
        *   [**1.3.1.** The APSR, CPSR, SPSR, and the Difference Between Them](https://lioncash.github.io/ARMBook/the_apsr,_cpsr,_and_the_difference_between_them.html)
            
    *   [**1.4.** VFP](https://lioncash.github.io/ARMBook/vfp/README.html)
        *   [**1.4.1.** VFP Registers](https://lioncash.github.io/ARMBook/vfp/vfp_registers.html)
            *   [**1.4.1.1.** VFP System Registers](https://lioncash.github.io/ARMBook/vfp/vfp_system_registers.html)
                *   [**1.4.1.1.1.** FPSID](https://lioncash.github.io/ARMBook/vfp/fpsid.html)
                    
                *   [**1.4.1.1.2.** FPSCR](https://lioncash.github.io/ARMBook/vfp/fpscr.html)
                    
        *   [**1.4.2.** Flush-To-Zero Mode](https://lioncash.github.io/ARMBook/vfp/enabling_flush-to-zero_mode.html)
            
        *   [**1.4.3.** Default NaN Mode](https://lioncash.github.io/ARMBook/vfp/default_nan.html)
            
*   [**2.** ARM946E-S](https://lioncash.github.io/ARMBook/arm946e-s/README.html)
    *   [**2.1.** CP15](https://lioncash.github.io/ARMBook/arm946e-s/cp15.html)
        *   [**2.1.1.** ID Code Register](https://lioncash.github.io/ARMBook/arm946e-s/id_code_register.html)
            
        *   [**2.1.2.** Cache Type Register](https://lioncash.github.io/ARMBook/arm946e-s/cache_type_register.html)
            
        *   [**2.1.3.** Tightly-coupled Memory Size Register](https://lioncash.github.io/ARMBook/arm946e-s/tightly-coupled_memory_size_register.html)
            

*   [Published using GitBook](http://www.gitbook.io/)
    

[](https://lioncash.github.io/ARMBook/GLOSSARY.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html#)
[](https://lioncash.github.io/ARMBook/GLOSSARY.html)

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[Nintendo 3DS ARM Documentation](https://lioncash.github.io/ARMBook/)

======================================================================

---